1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can provide stable read-out characteristic irrespectively of a change in a manufacturing process when a stored data is read from each of the memory cells in a memory array integrated with a high density.
2. Description of the Related Art
In the field of an LSI memory, a previously known non-volatile semiconductor memory includes a mask ROM, PROM (Programmable ROM), EPROM (Erasable and Programmable ROM), EEPROM (Electrical Erasable and Programmable ROM), etc. Particularly, the EPROM or EEPROM detects a change in the threshold voltage by a control gate according to whether or not there are charges stored in a floating gate, thereby storing data. The EEPROM includes a flash EEPROM (also referred to as "flash memory") that makes data erasure for the entire memory chip or for each block of a non-volatile semiconductor memory cell array, which is divided into some blocks.
The non-volatile semiconductor memory cell constituting the flash EEPROM is roughly classified into a split gate type and a stack gate type.
The split gate type of flash EEPROM is disclosed in WO92/18980 (G11C13/00).
FIG. 3 shows the sectional structure of the split-gate type non-volatile semiconductor cell 101 described in the publication (WO92/18980).
For example, an N-type source S and drain D are formed on a P-type single crystal silicon (Si) substrate 102. A floating gate FG is formed through a first insulating film 103 on a channel CH formed between the source S and the drain D. A control gate CG is formed through a second insulating film 104 on the floating gate FG. A part of the control gate DG is arranged through the first insulating film 103 on the channel CH and serves as a selecting gate 105. Storing electrons in the floating gate FG surrounded by the second insulating film 104 makes data storage.
FIG. 6 shows a read-out circuit for the above flash EEPROM. The sources of a pair of memory cells 51 and 52 are commonly connected to a source line SL. The respective control gates thereof are connected to word lines (row lines) WLa and WLb. The respective drains are connected to a single bit line BLa. A transistor 53 controlled by a column line CLa is connected to the bit line Bla.
Now, assuming that the word line WLa and the column line CLa have become an H level, the memory cell 51 is selected and connected to a voltage source Vdd through a load transistor 54. Then, a cell current Im corresponding to the stored data flows through the memory cell 51. The cell current Im is converted into a voltage by the load transistor 54 and the voltage is applied to the one input of a sense amplifier 55.
On the other hand, a reference cell 56 is provided. A voltage at the same H level as to the word line WLa is applied to the control gate of the reference cell 56. A prescribed reference current Ir flowing through the reference cell 56 is converted into a reference voltage Vref by a load transistor 57. The reference voltage Vref is applied to the other input of the sense amplifier 55. The sense amplifier 55 produces "1" or "0" which is a data stored in the memory cell 51 according to the comparison result between the voltage converted value V of the cell current and the reference voltage Vref.
In this way, using the sense amplifier, the read-out circuit amplifies the difference between the cell current flowing through the memory cell selected by the row line (word line) and column line and the reference current flowing through the reference cell so that the data stored in the memory cell is read.
As described above, the sources of the pair of memory cells 51 and 52 are commonly connected for the high integration of the memory cell array. Therefore, the source and drain in the memory cells 51 and 52 are arranged oppositely to each other by 180.degree. on a semiconductor substrate.
Referring to FIG. 7, a detailed explanation will be given of the pattern layout of the memory cells 51 and 52. Another pair of memory cells 51b and 52b, which are adjacent to the memory cells 51 and 52, are shown. The respective n+ sources thereof are commonly connected to a source line SL. The word lines WLa and WLb are unidirectionally extended so that they are partially carried on floating gates, respectively. The n+ drains 61 of the memory cells 51 and 52 are connected to a bit line Bla through contact holes 62 made above the n+ drains 61.
The bit line Bla is extended so that it is orthogonal to the word lines WLa and WLb. The adjacent pair of memory cells 51b and 52b have the same structure as the memory cells 51 and 52. An oxide film 63 for element isolation is formed between the adjacent pairs of the memory cells.
Meanwhile, although the memory cell array described above is efficient to implement high-density integration, it presents the following problem.
FIGS. 8A and 8B are sectional views taken in line X--X line in FIG. 7. If there is no mask drift between the word lines WLa, WLb and the floating gates 60, as seen from FIG. 8A, the lengths La abd Lb of the channel regions beneath the word lines WLa and WLb are equal to each other. Therefore, as long as the data storage state is the same for the memory cells 51 and 52, equal cell currents flow through the memory cells 51 and 52.
However, as seen from FIG. 8B, if the word lines WLa and WLb are displaced leftward for the floating gates 60, the lengths La' and Lb' of the channel regions immediately beneath the word lines WLa and WLb have a relationship Lb'&gt;La'. This is because the n+ drains 61 are formed by ion-implantation using the word lines WLa and WLb as masks. As a result, the cell current flowing through the memory cell 52 is smaller whereas that flowing through the memory cell 51 is larger. This presents a problem that the margin for the read of the memory cell 52 is decreased.
Referring to FIG. 9, this problem will be explained more concretely. FIG. 9 is a graph showing the operating points of a read-out circuit. The abscissa represents a voltage and the ordinate represents a current. Broken lines denote load curves of load transistors 54 and 57 and solid line denotes a current characteristic curve of the memory cells 51, 52 and reference cell 56 in their erased state (data "1").
The crossing point of the load curve of the load transistor 57 and the reference current characteristic curve of the reference cell 56 represents a reference voltage Vref. The crossing point of the load curve of the load transistor 54 and the cell current characteristic curve is a voltage-converted value of the cell current. Now it is assumed that there is mask drift as described above. Since the memory cell 51 and the reference cell 56 are oriented in the same direction, equal currents flow through these cells. Therefore, assuming that the voltage-converted value of the cell current of the memory cell 51 is V1, the cell current of the memory cell 52 decreases for the reference current so that the voltage converted value V1' of the cell current is shifted in a higher direction from V1 (V1'&gt;V1). As a result, the margin from the reference voltage Vref is decreased, thereby producing possibility of erroneously reading the data. This problem is an obstacle against making the arrangement of the memory cells that is suited to high-density integration.